Optimization of Chip Interconnect Area by using Interconnect Length and Width

This paper presents methodologies that provide better correlation between the apriori and posteriori estimation of interconnect length, width, area and power. A method to generate random realistic benchmark circuits for analysis is implemented. A prediction model that predicts the length, width, area and power of the benchmark circuit is developed. The net list is passed through the placement and routing phases to obtain the actual length. From the estimated length, the width, area and power are estimated. The effectiveness of the prediction technique used is validated from the results obtained. We postulate that the predicted area which comes out with a smaller error percentage than predicted length can be used as a termination condition in Simulated Annealing for placement. Results are compared for proving optimization with Lagrange’s Method.